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Micrel, Inc.
KSZ9692PB, KSZ9692PB-S
PCI Interface
The KSZ9692PB, KSZ9692PB-S integrates a PCI-to-AHB bridge solution for interfacing with 32-bit PCI, including
miniPCI, and cardbus devices where it is common for 802.11x-based Wireless products. The PCI-AHB bridge supports
two modes of operation in the PCI bus environment; host bridge mode and guest bridge mode. In the host bridge mode,
the ARM processor acts as the host of the entire system. It configures other PCI devices and coordinates their
transactions, including initiating transactions between the PCI devices and AHB bus subsystem. An on-chip PCI arbiter is
included to determine the PCI bus ownership among up to three PCI master devices.
In guest bridge mode, all of the I/O registers are programmed by either the external host CPU on the PCI bus or the local
ARM host processor through the AHB bus and the KSZ9692PB, KSZ9692PB-S can be configured by either the ARM or
the PCI host CPU. In guest bridge mode, the on-chip PCI arbiter is disabled. In both cases, the KSZ9692PB,
KSZ9692PB-S memory subsystem is accessible from either the PCI host or the ARM processor. Communications
between the external host CPU and the ARM processor is accomplished through message passing or through shared
memory.
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Compliant to PCI revision 2.3
Support 33 and 66MHz, 32-bit data PCI bus
Support 32-bit miniPCI or cardbus devices
Supports both regular and memory-mapped I/O on the PCI interface
AHB bus and PCI bus operate at independent clock domains
Supports big endian and little endian on AHB
PCI bus Round Robin arbiter for three external masters
Supports high speed bus request and bus parking
Dedicated DMA channel for bulk data transfer to/from DDR memory
Ethernet MAC Ports (Port 0 = WAN, Port 1 = LAN)
The KSZ9692PB, KSZ9692PB-S integrates two Gigabit Ethernet controllers that operate at 10, 100, and 1000 Mbps.
Each controller has an interface that can operate as MII or RGMII to an external 10/100 or 10/100/1000 PHY to complete
Ethernet network connectivity. An integrated 25 MHz clock eliminates external crystal or oscillator requirement for PHY to
reduce cost. Integrated 2-pin (MDC & MDIO) Station Manager allows ARM processor to access PHY registers and pass
control and status parameters. Wake-on-LAN is supported as part of the power management mechanism. Each port has a
dedicated MIB counter to accumulate statistics for received and transmitted traffic.
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IEEE 802.3 compliant MAC layer function
Configurable as MII or RGMII interface
RGMII interface compliant to Reduced Gigabit Media Independent Interface(RGMII) Version 1.3
MII interface compliant to Clause 22.2.4.5 of the IEEE 802.3u Specification
10/100/1000 Mbps half and full-duplex operation
Automatic CRC generation and checking
Automatic error packet discard
Supports IPv4 Header and IPv4/IPv6 TCP/UDP checksum generation to offload host CPU
Supports IPv4 Header and IPv4/IPv6 TCP/UDP checksum error detection
Supports 32 rules ACL filtering
Maximum frame length support is 2000 Byte at WAN port and 9K-byte at LAN port
Contains large independent receive and transmit FIFOs (8KB receive / 8KB transmit at WAN and 24KB receive / 22KB
transmit at LAN) for back-to-back packet receive, and guaranteed no-under run packet transmit
? Data alignment logic and scatter gather capability
? Configurable as MAC or PHY mode
? Separate transmit and receive DMA channels for each port
Wake-on-LAN
Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the network.
Examples of meaningful data include the reception of a Magic Packet, a management request from a remote administrator,
May 2011
37
M9999-051111-4.0
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